1. Field of the Invention
The present invention relates to a dynamic random access memory (DRAM) and in particular to a DRAM with vertical transistors and deep trench capacitors.
2. Description of the Related Art
With the wide application of integrated circuits (ICs), several kinds of semiconductor devices with higher efficiency and lower cost are produced based to meet different demands.
Typically a DRAM cell has one transistor and one is capacitor and memory capacity has reached 64 MB and can reach up to 256 MB. Therefore, to achieve increased integration it is necessary to reduce the size of memory cells and transistors to produce DRAM with higher memory capacity and processing speed. A three dimensional (3-D) capacitor structure can reduce the area occupied on a semiconductor substrate, and 3-D capacitors, such as deep trench capacitors, are applied in the fabrication of DRAM of 64 MB and above. A traditional plane transistor requires a large area of the semiconductor substrate and cannot satisfy the demands of high integration. Therefore, space saving, vertical transistors have become a trend in memory unit fabrication. A prevalent DRAM cell array integrates vertical transistors with trench capacitors.
Memory cells with vertical transistors and trench capacitors have several drawbacks as described below. As memory capacity is enhanced, more compact transistors and deep trench capacitors are necessary to satisfy the requirements of enlarged DRAM memory capacity. As shown in FIG. 1, the outdiffusion of dopants contained in the buried strap may merge and result in a short channel effect. Therefore, it is impossible to decrease the distance between the wordlines and deep trench capacitors to increase the integration of the DRAM.